1. Field of the Invention
This invention relates to an accelerometer. Specifically, the invention relates to an accelerometer chip having an added seismic mass to enhance its performance, and to the process used to fabricate the chip.
2. Description of the Prior Art
A schematic diagram of a prior art silicon accelerometer chip including a Wheatstone bridge is shown in FIG. 1. Eight resistors 10A, 10B, 10C, 10D, 10E, 10F, 10G, and 10H, are typically provided with two resistors in series in each arm of the bridge, although four resistors, with just one resistor in each arm can be used. A voltage V.sub.s (about +5 volts) is provided to terminal 12. Terminal 14 is grounded. An output voltage .DELTA.V is measured across terminals 16 and 18. Output voltage .DELTA.V is a function of the mechanical stress in the silicon substrate on which the resistors are formed, and the differing location of the resistors as shown by the arrows is such that in response to an acceleration which puts a mechanical stress on the silicon substrate, the magnitude and direction of the acceleration is sensed in terms of .DELTA.V.
In the prior art a three part silicon accelerometer chip as shown in FIG. 2 in cross section is typically provided to implement the circuit of FIG. 1. There is base layer chip 20, on top of which is provided the active chip layer 22, and on top of the active chip layer is the cover chip layer 24. The active chip layer includes a beam structure 26 in which are formed piezo resistors 28A, 28B, which form a part of a conventional Wheatstone bridge as described above. Deflection stops such as 30A, 30B are micro-machined in both the cover 24 and the base layers 20 to limit the amount of travel of the boss 32 and thus protect the beam 26 which supports the boss 32 from breaking in the event of over acceleration (i.e., shock). Metal pads such as 34 are provided on the active chip layer 22 for providing interconnection from the outside of the chip to the piezo-resistors 28A, 28B and thus to the Wheatstone bridge. Air gaps such as 36A, 36B are also provided between the cover layer 24 and the active chip layer 22 and between the active chip layer 22 and the base chip layer 20 to provide damping. A gap 37 is formed between the boss 32 and the surrounding periphery of the active chip layer 22. This device is typically formed by well known semiconductor processes.
It is known that the performance parameters sensitivity S and resonant frequency f of such a structure are interdependent. Both depend on the seismic mass M of the boss. S is proportional to M and f is proportional to 1.sqroot..sub.M. A low cost silicon accelerometer device requires a small chip size (typically four millimeter by four millimeter). This small chip size limits the seismic mass because the density of silicon is low (about 2.3 grams per cubic centimeter). For some applications, bridge-type accelerometers as shown in FIG. 2 having one or more beams spanning a gap have a favorable frequency response and cross sensitivity, but the sensitivity is limited and lower than the sensitivity of a cantilever type accelerometer having a single beam connected to a boss unsupported at one end. Thus the prior art device has less sensitivity than desired for most applications.
Also known in the prior art is a cantilever (i.e., a single beam) structure in a silicon accelerometer chip with a layer of metal such as gold deposited on top of the cantilever boss (or paddle) to provide a seismic mass, to make the chip more sensitive to acceleration.
This prior art approach has the drawback that it is difficult to manufacture in terms of alignment. Also, forming the metal layer requires additional semiconductor processing steps to deposit the metal. Also, such metal layer may interfere with the micro-machining of the mechanical (i.e., beam) structure.